1. Field of the Invention
The present invention relates to a data processing system, including a cache memory device and a shared memory area in a main memory, for converting a logical address into a physical address at high speed.
2. Discussion of the Prior Art
A conventional logical address cache memory device includes a cache data memory and a cache tag memory. The cache data memory stores a copy of a part of data stored in a main memory in units of blocks. The cache tag memory stores tag information associated with the data block. The tag information includes an address tag representing a logical address area assigned to a main memory physical address area corresponding to each data block stored in the cache data memory.
In a conventional logical address cache memory device, when a logical address for accessing a main memory is output from a CPU, the cache tag memory is accessed in accordance with the logical address, and an address tag corresponding to this logical address is retrieved. If the corresponding address tag is present in the cache tag memory and a cache hit occurs, the corresponding data block is read out from the cache data memory.
In a conventional data processing system including the above logical address cache memory device, a plurality of different logical addresses are often assigned to a given physical address area having a predetermined size in the main memory, i.e., a shared physical address area is often present. In this case, alias restriction is required. The alias restriction is defined such that lower n bits (n is determined on the basis of a capacity 2.sup.n bytes of the cache data memory) of a logical address associated with a physical address representing a shared physical address area of the main memory (to be referred to as a lower logical address hereinafter) are set to coincide with lower n bits of the physical address (to be referred to as a lower physical address hereinafter). In this manner, the main memory is managed in units of 2.sup.n bytes. In this case, upper bits except for the lower n bits of the logical address (to be referred to as an upper logical address) are used as an address tag of the cache tag memory.
In the data processing system having a shared memory area under the alias restriction, assume that a cache miss is detected in the logical address cache memory device in response to a main memory access request from a CPU. If the logical address area corresponding to the logical address to be accessed and the logical address area corresponding to the address tag obtained through the logical address are assigned to the same physical address area (shared memory area), even though the cache miss is detected, the object data block is stored in the cache data memory. In this case, it is wasteful to access the main memory as in the normal cache miss. Therefore, this data processing system generally includes a physical address coincidence detection mechanism to check if the above two logical address areas are assigned to the same physical address area.
A conventional physical address coincidence detection mechanism is always started upon detection of a cache miss in a logical address cache memory device. The upper logical address except for the lower logical address of the logical address to be accessed, and the address tag used for cache miss determination and output from the cache tag memory are converted into corresponding upper physical addresses, each of which is an upper address bit except for the lower physical address. The physical address coincidence detection mechanism detects whether the generated physical addresses coincide with each other. If no coincidence is determined, the main memory is accessed. However, when a coincidence between these physical addresses is detected, the object data block is stored in the cache data memory. Therefore, the cache data block from the cache data memory is used substantially as in a cache hit, and main memory access is inhibited. According to this system, when both the physical addresses coincide with each other, high-speed processing can be performed as compared with a system for unconditionally accessing the main memory upon detection of a cache miss. However, two logical/physical address conversion operations must be performed upon every cache miss. Therefore, when both the physical addresses do not coincide with each other, the processing speed is lowered as compared with the system for unconditionally accessing the main memory.